The invention relates generally to digital memory circuits and, more particularly, to the testing of configuration memories used for initializing Random Access Memory (xe2x80x9cRAMxe2x80x9d)  based programmable logic devices.
Field programmable gate arrays (xe2x80x9cFPGAxe2x80x9d) were first introduced by Xilinx, Inc. in 1985. An FPGA consists of cells that can be programmed to perform a variety of logical functions and programmable interconnects to connect the logic cells in a general way. The cells and interconnects are used to implement complex logical circuits. The use of FPGA""s continues to grow at a rapid rate due to their relatively short design cycles, reduced cost through logic consolidation, and the flexibility offered by their re-programmability.
In this regard, Xilinx, Inc. has developed a family of in-system programmable (xe2x80x9cISPxe2x80x9d) configuration memories. Such configuration memories are used for the initialization logic of static random access memory (SRAM) based FPGA""s such as, for example, the VIRTEX(copyright) AND SPARTAN(copyright) series of FPGA""s manufactured by Xilinx, Inc. of San Jose, Calif. The initialization logic customizes the FPGA through configuration data that is loaded into internal memory cells. The advantage that ISP configuration memories offer is that they can be re-programmed xe2x80x9cin-systemxe2x80x9d to accommodate last minute design changes and remote re-configurations without replacing or even removing the configuration memory from the system, which can be difficult and costly.
It is important that configuration memories, as well as other types of memory devices, be tested prior to shipment to ensure reliability. In this regard, the memories undergo a rigorous test regimen that seeks to verify the memory""s functional operation. One disadvantage of such a test regimen is that it can be complicated, difficult, and time-consuming, if not impossible, to implement on standard testing equipment. This is especially true for high density memories that can store mega or even giga-bytes of information. This situation is further compounded if conventional test equipment is not available or not capable of testing the memory device.
Two examples of conventional test equipment include the Topaz engineering tester manufactured by HILEVEL Technology, Inc. and the HP Versatest V1100 manufactured by Hewlett Packard. The Topaz tester is a logic tester with a limited vector memory and the HP Versatest V1100 tester has an algorithmic pattern generator. In this regard, neither tester includes a built-in capability for generating appropriate test bit patterns for the testing of large memory arrays and their address decoder circuitry. Therefore, a method of testing memories devices that does not suffer from the aforementioned drawbacks is highly desirable.
According to one embodiment of the present invention, a method of loading a memory device with a test bit pattern is provided. The method includes, for example, the steps of loading a data register with a first test bit pattern and storing the first test bit pattern in the memory device. The method also includes the steps of generating a new test bit pattern by shifting the first test bit pattern by a predetermined number of bits and storing the new test bit pattern in the memory device. The step of shifting the first test bit pattern by a predetermined number of bits includes, for example, the step of pushing a one or two-bit pattern into the first test bit pattern. The remaining test bit patterns for the memory device are similarly generated by pushing a one or two-bit pattern into the previously generated test bit patterns. Each test bit pattern is stored in the memory device after it is generated until the entire memory device has been programmed with the appropriate test bit pattern. The memory of the memory device is then decoded or read to verify proper implementation of the test bit pattern.
According to another embodiment of the present invention, a method of loading a memory device having a plurality of memory cells organized by rows and columns with a test bit pattern is provided. The method includes, for example, the steps of generating a first test bit pattern by loading a data register with two rows of bit information and storing the first test bit pattern in two rows of the memory device. The method further includes the steps of generating a new test bit pattern for two additional rows by shifting the first test bit pattern by at least two bits within the data register, wherein the step of shifting includes pushing a two-bit pattern into the data register. Once the new test bit pattern is generated, it is stored in the two additional rows. The method continues to generate new test bit patterns for the remaining rows by continuing to shift the test bit pattern resident in the data register by at least two bits by pushing the same two-bit pattern into the data register.
Hence, it is an advantage of the present invention to provide a method of generating test bit patterns without having to individually load entire test bit patterns for each row of a memory array into a data register.
It is another advantage of the present invention to provide a method of generating test bit patterns for memory devices that employs looping logic that pushes a limited number of bits into an existing test bit pattern to create a new test bit pattern.